To find out the details of the gate-based Pierce oscillator I recommend reading the references listed below. What follows is just a summary of the tips and formulas culled from the said references, pointers and tidbits which I found useful in getting a crystal-based oscillator up and running. I also did a number of breadboarded experiments and the results are shown below.
The following schematic shows the basic Pierce oscillator based on a CMOS inverter as its amplifier.
INV is of course the inverter (buffered or unbuffered). Oscillator signal is taken from the inverter output (Vout). To improve (decrease) its rise/fall time, another inverter or, better yet, a (fast!) Schmitt trigger can be used to spruce up the signal. The signal at the inverter input is a sinusoid and can also be used (some Microchip MCU datasheets show the clock signal being derived from the input of the inverter while other Microchip datasheets show it being taken from the inverter output).
Rf is a feedback resistor that puts the gate in linear (as opposed to digital) mode operation. The following table provides a rule of thumb value for Rf given crystal frequency:
Among other things, Rs limits the amount of crystal drive--increasing Rs decreases drive. A ballpark figure or first cut value for Rs can be derived by computing for and equating Rs to the reactance of Cb:
Xcb = 1/(2πfCb), where f = crystal frequencyAccording to Microchip:
Rs is typically 40 K ohms or less, but is almost never more than 100 K ohms. If the value for Rs is too high, then the high impedance input side of the amplifier may be more susceptible to noise, very much the same way a pull-up resistor on an input pin is normally kept below about 50 K ohms to prevent noise from having enough strength to override the input.Freescale (Motorola) meanwhile claims that for low frequencies such as 32.768kHz watch crystals, Rs can go as high as 330Kohms. Because of a permissible maximum drive of just 1µW, a minimum Rs value for tuning fork crystals such as the 32.768kHz crystal is 10kohm.
Ca and Cb along with Rs and XTAL provide a 180 degree phase shift (INV provides the other 180 degrees for a total of 360). Moreover, the Rs and Cb network partly "acts as a low pass filter that discourages the crystal from running at a third or fifth harmonic, or other higher frequency" (Lancaster and Berlin). Increasing Ca and Cb decreases the gain. Ca and Cb are usually equal but Cb can be made larger than Ca. The voltage at the input of INV is (partly) determined by Cb / Ca, so that increasing Cb relative to Ca increases the voltage at INV input. As a rule the values of Ca and Cb should satisfy the following condition:
Cload = (Ca)(Cb)/(Ca + Cb) + stray capacitancewhere Cload is the load capacitance of the crystal as per manufacturer's specifications. Typical load capacitances are 12 pF, 15 pF, 18 pF, 20 pF, 22 pF and 32 pF.
Finally, an advice worth keeping in mind: "Oscillator design is an imperfect art at best. Combinations of theoretical and experimental design techniques should be used." And so we move on to the experimental side of things.
I performed a few tests on a breadboard using 4.000 MHz and 32.768 kHz crystals. The values for the resistors and caps are the ones I arrived at after some trial and error. The values below seem to work better. Yes, that's a very subjective assessment and shall leave it at that.
I. Motorola MC14049UBCP hex inverting buffer
A. XTAL = 32.768 kHz
Rf = 10Mohm
Rs = 100kohm
Ca = 33pF
Cb = 50pF
Oscilloscope setup
Channel 1 (yellow) hooked up to INV2 output
Channel 2 (cyan) probe hooked up to Cb
CH1: INV2 output
CH2: INV1 output
CH1: Cb
CH2: INV1 output
I increased the capacitances as follows
Ca = 18pF
Cb = 100pF
and I was pleasantly surprised to see that the waveforms became much more stable--it practically ceased "wiggling" (the frequency was stable but the duty cycle wasn't and so the falling edge would be shifting rapidly to and fro horizontally--I was triggering on the rising edge so that wasn't moving at all)
CH1: INV2 output
CH2: Cb
Notice how the increasing the Cb to Ca ratio has decreased the signal's amplitude at Cb.
B. XTAL = 4.000 MHz
Rf = 5.1Mohm
Rs = 2kohm
Ca = Cb = 18pF
CH1: INV2 output
CH2: Cb
The CMOS 4000 series is relatively slow. In the reading above rise time is almost 37ns.
CH1: INV2 output
CH2: INV1 output
CH1: Cb
CH2: INV1 output
II. National Semiconductor MM74HC02N quad 2-input NOR gate. Unfortunately, I don't currently have any CMOS HC or AC series inverters. According to the datasheet each NOR gate is buffered as follows:
Using a buffered gate in a Pierce oscillator consumes less power and has a gain in the order of thousands compared to an unbuffered gate which has a gain of hundreds. The drawback of a buffered gate is that it is more sensitive to the values of the passive components and tends to be less stable.
A. XTAL = 32.768 kHz
Rf = 10Mohm
Rs = 51kohm
Ca = 33pF
Cb = 100pF
CH1: NOR2 output
CH2: Cb
I believe the over- and undershoots (at the rising and falling edges) is confusing the scope. In the screenshot above it's 40.98kHz, but in real time it's all over the place, sometimes reaching as high as 80kHz. So I turned on the cursors. As you can see it says 32.89kHz. Resolution is such that moving the cursor just one pixel down results in a reading of 32.68kHz.
To obtain a slightly better reading I sent the INV2 output to a Goldstar FG-2002C function generator / frequency counter. The LED display has a resolution to two decimal places and said the signal was 32.77kHz. I guess the output is pretty close to the crystal's fundamental frequency. The frequency counter apparently loads the INV1 output because connecting it directly produces garbage readings (bounces around from 40 to 65kHz). A minimum of 15 ohms of resistance or a few picofarads (the smallest I have right now is 18pF) of capacitance in series is enough to satisfy INV1. The reading is the same as probing INV2 output.
CH1: NOR2 output
CH2: NOR1 output
CH1: NOR2 output
CH2: VDD
CH1: NOR1 output
CH2: Cb
Changing the time base and capturing those overshoots/undershoots:
CH1: NOR1 output
CH2: Cb
Trigger: rising edge, 1.0V
CH1: NOR1 output
CH2: Cb
Trigger: falling edge, 4.0V
B. XTAL = 4.000 MHz
Rf = 5.1Mohm
Rs = 10kohm
Ca = Cb = 33pF
CH1: NOR2 output
CH2: Cb
CH1: NOR2 output
CH2: NOR1 output
CH1: Cb
CH2: NOR1 output
It turns out that the scope probe might be (largely) responsible for the ringing in the output. When not probing either INV1 or INV2, VDD has much less ripple and the ripple in Cb signal practically disappears:
CH1: Cb
CH2: ground
CH1: NOR2 output
CH2: VDD
CH1: Cb
CH2: VDD
References:
- Don Lancaster and Howard M. Berlin, CMOS Cookbook, 2ed., Howard W. Sams, 1988, p.279-281
- AN849: Basic PICmicro® Oscillator Design
- Pierce-Gate Crystal Oscillator, an Introduction
- AN1706/D Microcontroller Oscillator Circuit Design Considerations
- SZZA043: Use of the CMOS Unbuffered Inverter in Oscillator Circuits
- AN340: HCMOS Crystal Oscillators
Was your scope probe on 10x and also was probe 'capacitor tuned for a perfect square wave output/ high frequency attenuation?
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