I've been googling and the half dozen designs or so of automatic night light circuits I've seen have been very basic--low parts count and usually use only discrete transistors--and, more critically, are prone to at least two conditions:
1. "Chattering", whereby when ambient light level is at or is crossing the trip point for the load switching, the relay/load can rapidly turn on and off, the reason being that there’s no hysteresis built into the circuit. Hysteresis in this case means that the ambient light level at which the load is turned on is slightly lower than the level at which it is switched off. This difference in trip points eliminates any oscillations when the trip point is crossed, specially considering that sunlight / sky light level increase/decrease extremely slowly relative to electronic switching speeds.
2. A transient, high amplitude and fast rising/falling ambient light level will make the circuit switch the load on/off (depending on whether the light level change is positive or negative). For example, at night, lightning and head lamps of passing vehicles can fool the circuit into interpreting the brightness as indicative of daytime and turn off the load for the duration of the high ambient light level. In light of this (pun intended), there’s a need for a low pass filter so that the circuit rejects such transients. An RC network of sorts will thus be necessary.
The very first viable automatic night light switch (ANLS) I designed back in 2002 already incorporated both these features. That is, it had hysteresis and a low pass filter. The circuit is based on a quad NOR CMOS IC, with two of the gates configured as an RS flip flop. Another gate is used an inverter and the other hooked up to the output of the flip flop and functions as an inverter buffer. NAND gates would function just as well. I chose NOR because they were slightly cheaper. All circuits that I've installed (controlling the perimeter lights of my home) which use this flip flop design employ NOR gates.
I used CMOS instead of TTL for the very important reason that CMOS gates have very high input impedance [Note 1]. Given that the LDR voltage divider will have a very high impedance (Mohms) it is necessary that the gate not load it down. The essentially open circuit of CMOS inputs accomplishes this well. CMOS also has an elegant feature--its output changes state when the voltage at the input is exactly half the supply voltage [Note 2]. This makes designing and calculation of the voltage divider a breeze.
In 2003 I wrote a couple of papers documenting the circuit. I'm reproducing both below with slight editing.
Notes:
1. "The inputs to all [CMOS] devices are open circuits." (Lancaster, D., and H. M. Berlin.
CMOS Cookbook. 2ed. Indianapolis,Ind.: Howard W. Sams, 1988. p.11.)
2. "The output of the [CMOS] inverter will change state whenever Va [voltage of the voltage divider] crosses the (V+)/2 point [V+ = Vdd]." (Carr, Joseph J..
IC User's Casebook. Indianapolis, Ind. USA: Howard W. Sams, 1988. p.235.) "The logic changes from high to low exacly halfway up to the supply voltage." (Lancaster p.11.)
------------
Design of Ambient Light Activated Switches
January 2003
The following document describes the operation of a circuit first designed in May 2001 as well as derivatives of that circuit. All the circuits are designed to switch a load on when ambient light condition drops to a certain level, and turn off the load when light condition rises to a certain level. The level at which switching occurs is variable. The circuits can be used to automatically switch on outdoor lights at dusk and switch them off at dawn.
Fundamentals
CMOS 2-input NAND or NOR gates are used to create a simple RS latch and inverters. Two gates are used as voltage comparators whose outputs toggle high or low. CMOS gates (CD4000 series) are inherently referenced to 50% of supply voltage such that an input greater than 50% of supply is interpreted as a high, while an input less than 50% is detected as a low.
By using a light dependent resistor (LDR) in series with fixed value resistors a voltage divider can be formed. Since the resistance of an LDR varies in proportion to incident light, we set up the resistor network such that LDR resistance will be 50% of total series resistance at the light level at which the load should be switched on.
To create a practical circuit and one wherein the RS latch does not enter into oscillation, we build hysteresis into the circuit by setting the switch-on light level to be different from the switch-off level. This can be accomplished by adding a small resistance in series with the LDR so that switch-off resistance value (and, therefore, voltage value) is greater than for switch-on.
The only feasible simple circuit with hysteresis is one that turns the load on when ambient light level drops to less than L and can only be turned off when light level becomes greater than L. The difference between these two light levels is the hysteresis band. A representation of the hysteresis curve is given below. Assuming load is off the circuit will switch it on only when light level drops to L
on and thereafter will be on as light level decreases further. When light level increases load will not be switched off until ambient conditions reaches point L
off after which the load will remain off as long as light level does not drop below L
on. It is not possible to build a simple circuit wherein the load is switched on a certain light level and then switched off at an even darker condition.
Below is a basic sense and control circuit of a light activated switch using CMOS gates (NOR gates in this case). A voltage divider network formed by reference resistance R
R, hysteresis resistance R
h, and LDR.
Given the above voltage divider, reset point is given by the equation:
\[
V_{off} = \frac {R_h + R_L} {R_R + R_h + R_L} > 0.5
\]
where
R
R = Reference resistance
R
h = Hysteresis resistance
R
L = LDR resistance
But because of NOR.a is configured as an inverter, NOR.b actually senses a low when V
off is greater than 50% voltage.
Set point is the voltage at which the load is turned on and is given by:
\[
V_{on} = \frac {R_L} {R_R + R_h + R_L} > 0.5
\]
Because of inverter NOR.a set input of the latch will be low when reset input is high and vice versa, except when ambient light conditions fall within the hysteresis band. In that transition period both inputs will be low. Thus, the latch outputs will be locked and cannot change.
By increasing the value of R
h the difference between light level at which the circuit turns on and off increases, i.e., the hysteresis band widens. However, this also means that the load will be switched off at higher ambient light conditions. Because of this R
h would be, for practical purposes, less than 10% of R
R, with a value between 1% to 5% being sufficient.
By increasing R
R the circuit is forced to turn on at darker ambient condition. For outdoor ambient lighting detection R
R may take on a value between 500K to 1Mohm given the particular LDR used. Other types of LDRs may necessitate different R
R values. By using a variable resistor, field adjustment of the circuit is possible.
IMPORTANT: R
R should be such that ambient light has not reached its minimum level, else the circuit will become too sensitive to slight increases in ambient conditions (even with R
h) which may then trigger the circuit to turn off the load.
One important consideration in building a practical outdoor ambient light-activated switch is the occasional occurrence of large and abrupt but transient variations in light level. For instance, such phenomena as lightning may trigger the circuit to turn on for the duration of the lightning flash and then turn off again immediately thereafter. It is, therefore, necessary to shield the circuit by adding an RC network to buffer such changes. This is the purpose of capacitor C3 in the circuit below. C3 is charged via R
R and remains at a voltage level determined by R
h + R
L. As LDR resistance varies with light level C3 charges/discharges. When light condition changes gradually (the normal state) C3 charges/discharges only by a small amount and so voltage across C3 follows that across R
h + R
L nearly instantaneously. But during an abrupt change--say, LDR resistance changes by a factor of 10 or more in a fraction of a second--voltage across C3 will not immediately drop or increase. There will be a time lag before voltage across C3 will settle. This lag prevents the voltage at NOR.a input from changing immediately.
The problem with the above design is that it creates a much greater time lag for the load to be turned on again than for it to be turned off. Thus, during, for instance, a lightning flash at night, LDR will drop to a low value such that LDR + R
h resistance will be a fraction of R
R. This means that capacitor discharge RC time is shorter than charging RC time. Yet what we require is for discharge time to be significant to prevent the circuit from reacting to sudden increases in ambient light level.
To remedy this lopsided (and undesirable) response/performance of our circuit we need to find a way to increase the amount of resistance through which C3 is discharged without affecting the voltage divider and without increasing (if possible) the resistance through which C3 is charged. This can be accomplished by using the setup below.
A resistor and a signal diode in parallel have been added. In this arrangement C3 is charged via RR but discharges through R
d + R
h + R
L. Hence, the minimum resistance by which C3 can discharge is R
d + R
h. By simply increasing R
d we can "desensitize" our circuit to large, abrupt and transient increases in light level however much we want to.
Here is how the circuit works:
When light level has settled C3 is neither charged nor discharged. When light level decreases C3 is charged via R
R. Because of diode D2 R
d is shunted. Therefore, the time for C3 to charge is a function of R
RC3. When light level increases LDR resistance decreases forcing C3 to discharge. In this case D2 is reverse biased and so C3 discharges via R
d. The discharge time is a function of (R
d+R
h+R
L)C3.
When there is a sudden increase in ambient light conditions LDR will dip to a very low resistance level. Without R
d capacitor discharge would be very fast since the only resistance left would be R
h; hence, the load will be turned off soon thereafter if ambient condition does not return to "normal" quick enough. Without R
d and with C3 = 100uF load turn off occurs within a second or two when light level condition varies from very dark to very bright. By choosing R
d to be approximately equal to R
R the charge and discharge times of C3 can be made roughly equal. Or by making R
d very large the circuit can be made insensitive to ambient conditions suddenly getting very bright for a long period of time. For example, given C3 = 47uF and R
d = 1Mohm and a sudden transition from near total darkness to midday light level, tests show that the circuit will not turn off the load until after around 30 seconds of continual exposure to the light source. With such capacitor and resistor values the circuit will be totally immune to false turn-offs even during the severest lightning storms.
While the circuit above uses NOR gates, NAND gates may also be employed to the same end. When using NOR gates the inputs to the RS latch must both be low when within the hysteresis band. In a NAND-based circuit on the other hand both must be high when ambient light conditions are within the dead band. These conditions are necessary for these two respective latches to operate properly. Inputs to a NOR latch cannot both be high simultaneously, while inputs to a NAND latch cannot both be low at the same time. In the circuit above such a condition cannot arise because of NOR.a inverter and R
h.
Operation of NOR-Based Circuit
The operation of the NOR-based switch has been covered in detail above. To recapitulate: R
R, R
h and R
L form a resistor network and, hence, a voltage divider. NOR.a is used as an inverter. NOR.b and NOR.c gates form an RS latch. Assume that output of NOR.b is initially low (load is off). When light level falls such that LDR resistance is just over 50% of R
R+R
h+R
L (= R
total) NOR.c output goes low and forces NOR.b to output high, thus turning the load on. NOR.b output will remain high as light levels decrease. Thereafter, when ambient light level begins increasing LDR resistance will decrease to below 50% of R
total. Output of NOR.b, however, will not go low until R
h+R
L goes below 50%. Therefore, a higher light level is necessary for load turn-off than for load turn-on. This hysteresis is necessary to avoid latch race conditions and to prevent rapid switch on-off of load during the 50% mark crossover.
Operation of NAND-Based Circuit
A NAND-based switch is analogous to a NOR-based circuit but a NAND latch needs low inputs to force output latch high, while race condition occurs when both inputs are low simultaneously. Because of these characteristics the inverter is connected to the LDR instead and output is drawn from NAND.c when an NPN transistor is used (output of NAND.b can be used if a PNP transistor is used).
In the circuit below R
R, R
h and R
L form a resistor network and, hence, a voltage divider. NAND.a is used as an inverter. NAND.b and NAND.c gates form an RS latch. Assume that output of NAND.c is initially low (load is off). When light level falls such that LDR resistance is just over 50% of R
R+R
h+R
L (= R
total) NAND.a output goes low and so NAND.c output goes high, thus turning the load on. NAND.c output will remain high as light levels decrease. Thereafter, when ambient light level begins increasing LDR resistance will decrease to below 50% of R
total. Output of NAND.b, however, will not go high until R
h+R
L goes below 50%. Therefore, a higher light level is necessary for load turn-off than for load turn-on.
Load Switching
Output of either NAND or NOR gate based circuit is used to turn on a transistor which then triggers a triac to turn on. Attention should be paid to the required gate trigger current of the particular triac used. Enough current should be delivered to the triac gate to assure full switch-on of the triac even in the 4th quadrant which usually requires a much higher gate current. Transistor should be a high gain type so as not to unduly load the CMOS gate if output is obtained from one of the gates that form the latch.
One important consideration when using triacs is the quadrants in which the triac will be operating (see diagram below). With triac optocouplers the triac is triggered by alternating positive and negative currents. This is called "in-phase triggering" since gate polarity with respect to MT1 always follows that of MT2 polarity vs. MT1. Therefore, the triac operates in Quadrants 1 and 3.
With DC triggering, gate voltage with respect to MT1 will either be always positive or always negative. If positive, the triac will be operating in Quadrants 1 and 4. If gate to MT1 voltage is always negative then triac will be working in Quadrants 2 and 3. In other words, when the gate is sourcing current (trigger current always flows from gate to MT1) then the triac is operating in Quadrants 1 and 4. When the gate is sinking current (current flows the more positive MT1 to gate) then the triac is operating in Quadrants 2 and 3.
We can design our ambient light-activated switch to trigger the triac with either positive or negative DC gate current. The circuits below show how an NPN and a PNP transistor can trigger a triac given a logic high or low respectively. With a logic high the collector to emitter junction of the NPN transistor conducts and triggers the triac. With a logic low the emitter to collector junction of the PNP transistor conducts and triggers the triac. Because the gate in either configuration is always positive with respect to MT1 the triac in both circuits will be operating in Quadrants 1 and 4.
According to Teccor's data sheet its Q401E3 1A 400VAC triac needs typically 50mA for Quadrant 4 operation. Our transistor must thus be able to source at least this much current, preferably more. In the circuit S9013 and S9012 transistors are assumed to have an h
FE of 100 at collector currents less than 100mA. Therefore, a minimum base current of 0.5mA is required for collector to source at least 50mA. R1 is chosen to provide this minimum base current. R2 on the other hand limits the actual current that is fed to the triac gate.
Because triacs require substantially greater gate current in Quadrant 4 it is best to operate a triac only in Quadrants 1, 2, and 3. Current requirements is of great concern in our circuit because the power supply can source only around 80mA maximum. Therefore, operating the triac in Quadrants 2 and 3 via negative DC gate current is very much preferred. This can easily be achieved by making the positive side of the DC supply the common leg for DC and AC supplies and tying MT1 to it. The net effect is that triac gate will be sinking current to trigger the triac instead of sourcing it--the reverse of the preceding circuits. The circuits below illustrate how this can be achieved using transistors. Using an NPN transistor a logic high will trigger the triac. With a PNP transistor a logic low will trigger it.
Any triac may be used which requires a maximum gate trigger current of less than 80mA--the approximate upper limit of the power supply. TO-220 packaged triacs may need a heat sink.
The Teccor Q401E3 needs a maximum of 25mA gate trigger when the triac is operated in Quadrants 1 to 3. This must be the minimum current supplied to the triac to ensure proper turn-on. Supplying a current greater than this is preferred.
The relationship between collector and base current is given by the following equations:
\[
I_C = I_B h_{FE}
\]
\[
I_B = \frac {V_S - V_{BE}}{R_B}
\]
Therefore:
\[
I_C = \frac {V_S - V_{BE}}{R_B} h_{FE}
\]
where
I
C= collector current
I
B = base current
h
FE = minimum transistor current gain
R
B = current limiting resistance for base
V
S = input voltage at base, usually power supply voltage
V
BE = voltage across base and emitter with base saturated
Assuming collector current provided by base current is greater than current needed by load, current limiting resistor for fixed-voltage load that requires a current source (e.g., the triac gate) is derived as follows:
\[
I_L = \frac {V_S - V_{CE}}{R_L}
\]
where
I
L = current required by load
V
S = power supply voltage
V
CE = voltage across collector and emitter with base saturated
R
L = current limiting resistor in series with load
Given a S9013 NPN or S9012 PNP transistor as output amplifier to switch the triac on, we can derive the necessary resistor values.
To make 50mA available to the triac gate we choose the base current limiting resistor as follows:
I
C = 50mA
S9013 minimum h
FE = 60
V
S = 5.6V
V
BE = 1V
Using the above equations base resistor R
B = 5.5Kohm. We choose a standard 5.1Kohm resistor
To limit the actual current supplied to the triac gate to 50mA we choose the collector current limiting resistor as follows:
I
L = 50mA
V
CE = 0.6 (max.)
Using the above equations R
L = 100 ohms
LED's are shown in the circuit but are optional. They provide visual feedback as to the state of the RS latch. Since NOR/NAND gates can only source or sink very small currents, the current limiting resistors for the LED's must limit current to less than 2mA.
Power Supply
The circuit utilizes a half-wave transformerless power supply with one leg of the AC line common with DC positive supply. Filter capacitor C2 must be large enough to supply enough gate trigger current to the triac during the negative half cycle. The working DC voltage should be above 3V for the CMOS gates to work properly but should be low enough so that Zener diode Z1 does not dissipate too much power during the positive half cycle when it is reversed biased, during daytime when load is turned off and practically all current is being dissipated by the Zener.
It is important to note that when reverse biased D1 is blocking the full AC line voltage. Therefore, for a 240VAC line it must have a peak inverse voltage (PIV) rating greater than 340V. A 1N4004 will suffice. But using a diode with a much higher PIV rating--600V 1N4005, for example--may be a better idea to provide added protection for the other devices in the circuit from voltage spikes during the negative half cycle.
Adding a fuse in series with the AC line offers added protection in case of overload, shorts or breakdown of C1.
References:
Triac Operation:
Motorola Thyristor Device Data, 2ed. Motorola Inc. 1988.
Teccor triac catalog
Transistor as Switch:
David A. Bell.
Solid State Pulsed Circuits, 2ed. Reston. 1981.
Robert Boylstad & Louis Nashelsky.
Electronic Devices, 4ed. Prentice-Hall. 1987.
------------
Mathematics of CMOS NOR Latch Based Auto Night Light Switch
July 2003
The design of an auto night light switch based on CMOS NOR gates was discussed in a January 2003 paper. The mathematics involved in the voltage divider is discussed in further detail here.
The following circuit shows the voltage divider network and the latch composed of 2-input NOR gates. NOR.a is used an inverter, while NOR.b and NOR.c are wired as a latch. R
d, D2 and C2 form a dampening RC network that prevents the circuit from reacting to abrupt and transient changes in light levels.
We will determine the LDR resistance at which the output of NOR.b goes high and low, i.e., when the load is turned on (output high) and when NOR.b output goes low, i.e., when the load is switched off (output low). We will also determine the hysteresis band between turn on and turn off.
We know that the inputs of the 4000 series CMOS gates are referenced to 50% of supply voltage (V+), meaning that voltages < 0.5V+ are interpreted as low, and voltages > 0.5V+ are interpreted as high.
In the above circuit R
R, R
h and LDR form a voltage divider.
Let
R
L = resistance of LDR
R
Lon = resistance of LDR at the instant R
L = 50% of total resistance (load is switched on)
R
Loff = resistance of LDR at the instant R
L + R
h = 50% of total resistance (load is switched off)
Because NOR.b and NOR.c are wired as a latch the circuit will turn on the load (NOR.b output goes high) when voltage at the input of NOR.c becomes greater than 50% V+, or in other words R
L is greater than 50% of total resistance (input of NOR.b must be low or a disallowed state ensues). The transition point is therefore:
\[
\frac {R_L_{on}} {R_R + R_h + R_L_{on}} = \frac {R_R + R_h} {R_R + R_h + R_L_{on}} = \frac {1}{2}
\]
\[
R_L_{on} = R_R + R_h
\]
On the other hand, the circuit will turn off the load (NOR.b output goes low) when input at NOR.a (used an inverter) goes below 50% V+, or in other words R
L+R
h is less than 50% of total resistance (input of NOR.c must be low or a disallowed state ensues). The transition point is thus:
\[
\frac {R_L_{off} + R_h} {R_R + R_h + R_L_{off}} = \frac {R_R} {R_R + R_h + R_L_{off}} = \frac {1}{2}
\]
\[
R_L_{off} = R_R - R_h
\]
The hysteresis band is the difference between and R
Lon and R
Loff :
\[
h = R_L_{on} - R_L_{off}
\]
\[
h = 2R_h
\]
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Note: LaTeX math code was embedded using
mathcache
