Remember that strange phenomenon on the dual voltage I2C bus where I was getting 3.4V on the 2.8V bus and 4V on the 5V bus? Well, I finally found the culprit. Turns out that I had, with breathtaking unparalleled stupidity, plugged the two TO-92 2N7000 MOSFETs the wrong way around! The drain and source pins got reversed! So all the while when the bus was idle, current was flowing from the 5V rail to the 2.8V I2C bus (due to the inherent diode in MOSFETs). Almost certainly protection diodes on the MMA7660FC accelerometer chip were conducting, thus giving that extra 0.6 to 0.7V excess voltage reading. Because the chip is still ticking the current flowing through it must've been within limits. Had I decreased the pull-up resistors to below 1kohm, it (and therefore I) may not have been so lucky.
Interestingly, as we've seen, I2C communication works even with this reversed set up--with the lower voltage on the MOSFET drain side and the higher voltage bus on the source side. Let's analyze the circuit to see how and why it works. (We'll consider only one line since the explanation applies to both SDA and SCL.)
A. When neither the 7660 nor the MCU is pulling the line low--i.e., Q1 and Q2 are off--then MOSFET Q0 is off--because its source pin is at a higher voltage than the gate. Points V1 and V2 ought to be pulled up to VDD1 and VDD2, respectively. But due to Q0's internal diode--with the anode at VDD2 (5-volt) side--current flows from VDD2 toward VDD1 side. Since VDD2 > (VDD1 + diode voltage drop), the accelerometer's protection diode D1 conducts and so at point V1 we get a voltage less than VDD2 but greater than VDD1. We expect V1 = VDD1 + VFD1, where VFD1 = D1's forward voltage.
Because of Q0's diode we expect the voltage at point V2 = V1 + VFD0, where VFD0 = forward voltage of Q0's diode. End result is that both V1 and V2 are at logic high. Note that V2 may not reach a logic high if the voltage difference between VDD1 and VDD2 is large. For instance if VDD1 = 2.8V and VDD2 = 15V then, assuming the accelerometer hasn't been fried, the voltage at V2 would still be around 4V which may not be sufficient to meet the minimum voltage required for a logic high.
B. When Q2 turns on V2 is pulled to ground. Q0 source is likewise pulled to ground. Because the voltage difference between Q0's gate and source exceeds the gate threshold voltage VGS(th), Q0 switches on causing V1 to be pulled to nearly to ground as well. So both V1 and V2 are at logic low.
C. When Q1 turns on, V1 is pulled to ground. Because of Q0's internal diode V2 gets pulled down close to ground as well. (V2 will be approximately 0.7V, with the exact value depending on the voltage across Q1's drain and source). V1 and V2 are at logic low. [March 13 edit: V2 will actually be very close to ground because as in B above the voltage difference between Q0's gate and source exceeds the gate threshold voltage VGS(th) and thus Q0 turns on. With less than a couple of milliamps of current Q0 drain-source voltage is in the order of millivolts.]
I want to post the screenshots of the oscilloscope readings of the dual voltage I2C with the error corrected, but I still don't have my USB flash drive so I'll put the images up when I finally get it back.